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HD74LV240A Datasheet

  • HD74LV240A

  • Octal Buffers / Drivers with 3-state Outputs

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HD74LV240A
Octal Buffers / Drivers with 3-state Outputs
REJ03D0327鈥?300Z
(Previous ADE-205-272A (Z))
Rev.3.00
Jun. 23, 2004
Description
The HD74V240A has eight inverter drivers with three-state outputs in a 20-pin package. Four inverters are included in
one circuit. Each circuit can be independently controlled by the enable signal 1OE or 2OE, which enables outputs
when receiving a low-level signal. Low-voltage operation is suitable for battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
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鈥?/div>
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鈥?/div>
V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current 鹵8 mA (@V
CC
= 3.0 V to 3.6 V), 鹵16 mA (@V
CC
= 4.5 V to 5.5 V)
Ordering Information
Package Type
SOP鈥?0 pin (JEITA)
SOP鈥?0 pin (JEDEC)
TSSOP鈥?0 pin
Package Code
FP鈥?0DAV
FP鈥?0DBV
TTP鈥?0DAV
Package
Abbreviation
FP
RP
T
Taping Abbreviation
(Quantity)
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
ELL (2,000 pcs/reel)
Part Name
HD74LV240AFPEL
HD74LV240ARPEL
HD74LV240ATELL
Note: Please consult the sales office for the above package availability.
Function Table
Inputs
OE
L
L
H
Note: H:
L:
X:
Z:
High level
Low level
Immaterial
High impedance
A
H
L
X
Output Y
L
H
Z
Rev.3.00 Jun. 23, 2004 page 1 of 9

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