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HD74LV166AFP Datasheet

  • HD74LV166AFP

  • SHIFT REGISTER|LV-CMOS|SOP|16PIN|PLASTIC

  • 16頁

  • ETC

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HD74LV166A
Parallel-Load 8-bit Shift Register
ADE-205-268 (Z)
1st Edition
March 1999
Description
The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the
register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded
asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge
of either clock inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
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V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current
鹵6
mA (@V
CC
= 3.0 V to 3.6 V),
鹵12
mA (@V
CC
= 4.5 V to 5.5 V)

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