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HD74LV138AT Datasheet

  • HD74LV138AT

  • DECODER/DEMUX|3-TO-8-LINE|LV-CMOS|TSSOP|16PIN|PLASTIC

  • 9頁

  • ETC

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a
HD74LV138A
3-to-8 line Decoder / Demultiplexers
ADE-205-261 (Z)
1st Edition
March 1999
Description
The HD74LV138A is designed to be used in high-performance memory-decoding or data-routing applica-
tions requiring very short propagation delay times. The conditions at the binary-select inputs and the three
enable inputs select one of eight input lines.
Two active-low and one active-high enable inputs reduce the need for external gates or inverters when ex-
panding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires
only one inverter.
An enable input can be used as a data input for demultiplexing applications.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook comput-
ers), and the low-power consumption extends the battery life.
Features
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V
CC
= 2.0 V to 5.5 V operation
All inputs V
IH
(Max.) = 5.5 V (@V
CC
= 0 V to 5.5 V)
All outputs V
O
(Max.) = 5.5 V (@V
CC
= 0 V)
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.3 V (@V
CC
= 3.3 V, Ta = 25擄C)
Output current
鹵6
mA (@V
CC
= 3.0 V to 3.6 V),
鹵12
mA (@V
CC
= 4.5 V to 5.5 V)
Function Table
Enable Inputs
G1
X
X
L
H
H
H
H
H
H
H
H
G2A
H
X
X
L
L
L
L
L
L
L
L
G2B
X
H
X
L
L
L
L
L
L
L
L
Select Inputs
C
X
X
X
L
L
L
L
H
H
H
H
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Outputs
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L

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