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HD74HCT373RP Datasheet

  • HD74HCT373RP

  • LATCH|SINGLE|8-BIT|HCT-CMOS|SOP|20PIN|PLASTIC

  • 10頁

  • ETC

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HD74HCT373/HD74HCT533
Octal D-type Transparent Latches (with 3-state outputs)/
Octal D-type Transparent Latches (with inverted 3-state outputs)
Description
When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q
outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals
present at the other inputs and the state of the storage elements.
Features
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LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(Data to Q) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 碌A max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A max (Ta = 25擄C)
Function Table
Output Control
L
L
L
H
X :
Z :
Enable
G
H
H
L
X
D
H
L
X
X
HD74HCT373
Q
H
L
No change
Z
HD74HCT533
Q
L
H
No change
Z
Irrelevant
Off (high-impedance) state of a 3-state output.

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