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HD74HCT137RP Datasheet

  • HD74HCT137RP

  • DECODER/DEMUX|3-TO-8-LINE|HCT-CMOS|SOP|16PIN|PLASTIC

  • 8頁(yè)

  • ETC

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HD74HCT137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.
When
GL
goes from low to high, the address present at the select inputs (A, B and C) is stored in the
latches. As long as
GL
remains high no address changes will be recognized. Output enable controls, G
1
and G
2
, control the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G
1
is high and G
2
is low. The HD74HCT137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
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LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: t
pd
(A, B, C to Y) = 18 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 4.5 to 5.5 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)

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