HD74HC673 Datasheet

閱覽下載糾錯(cuò) 0

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

HD74HC673

16-bit Shift Register

Description

The HD74HC673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-

state input/output (data I/O) port to the shift register allows serial entry and/or reading of data. The storage

taking the store-clear input low. The storage register may be parallel loaded with shift-register data to

provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the

storage-register data upon command.

A high logic level at the chip-select (CS) input disables both the shift-register clock and the storage register

clock and places the data I/O in the high-impedance state. The store-clear function is not disabled by the

chip select.

Caution must be exercised to prevent false clocking of either the shift register or the storage register via the

chip-select input. The shift clock should be low during the low-to-high transition of chip select and the

store clock should be low during the high-to-low transition of chip select.

Features

鈥?/div>

High Speed Operation: t

(MODE/STRCLK to Y) = 23 ns typ (C

= 50 pF)

High Output Current: Fanout of 15 LSTTL Loads (Q

output)

Wide Operating Voltage: V

= 2 to 6 V

Low Input Current: 1 碌A(chǔ) max

Low Quiescent Supply Current: I

(static) = 4 碌A(chǔ) max (Ta = 25擄C)

建議反饋