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HD74HC597FP Datasheet

  • HD74HC597FP

  • SHIFT REGISTER|HC-CMOS|SOP|16PIN|PLASTIC

  • 10頁

  • ETC

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HD74HC597
8-bit Latch/Shift Register
Description
The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both
the storage register and shift register have positive-edge triggered clocks. The shift register also has direct
load (from storage) and clear inputs.
Features
鈥?/div>
High Speed Operation: t
pd
(SCK to Q
H
鈥? = 14 ns typ (C
L
= 50 pF)
鈥?/div>
High Output Current: Fanout of 10 LSTTL Loads
鈥?/div>
Wide Operating Voltage: V
CC
= 2 to 6 V
鈥?/div>
Low Input Current: 1 碌A(chǔ) max
鈥?/div>
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
RCK
SCK
X
X
X
X
X
X
X
X
X
SLoad
X
L
L
L
H
H
SCLR
X
H
H
L
L
H
Function
Data loaded to input latches
Data loaded from inputs to shift register
Data transferred from input latches to shift register
Invalid logic, state of shift register indeterminate when signals
removed
Shift register cleared
Shift register clocked Q
n
= Q
n 鈥?1
, Q
A
= SER

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