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HD74HC595FP Datasheet

  • HD74HC595FP

  • SHIFT REGISTER|HC-CMOS|SOP|16PIN|PLASTIC

  • 58.18KB

  • 10頁(yè)

  • ETC

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HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register and the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect
both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High Speed Operation: t
pd
(RCK to Q) = 17 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 15 LSTTL Loads (Q
A
to Q
H
outputs)
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
RCK
X
X
X
X
SCK
X
X
SCLR
X
L
H
H
G
H
X
X
X
Function
Q
A
to Q
H
high impedance
Shift register cleared Q
H
鈥?= L
Shift register clocked Q
n
= Q
n 鈥?1
, Q
A
= SER
Contents of shift register transferred to output latches

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