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HD74HC390 Datasheet

  • HD74HC390

  • Dual Decade Counters

  • 9頁

  • HITACHI

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HD74HC390
Dual Decade Counters
Description
The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-
five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-
quinary, or various combinations up to a single divide-by-100 counter.
The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each
has an independent clear input. When clear is set high all four bits of each counter are set to a low level.
This enables count truncation and allows the implementation of divide-by-N counter configurations.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High Speed Operation: t
pd
(Clock A to Q
A
) = 11 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
Clock
A
X
B
X
X
X
Clear
H
L
L
Operation
Clear
梅2
and
梅5
Increment
梅2
Increment
梅5

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