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HD74HC279P Datasheet

  • HD74HC279P

  • LATCH|QUAD|1-BIT|HC-CMOS|DIP|16PIN|PLASTIC

  • 9頁

  • ETC

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HD74HC279
Quad.
S鈥揜
Latches
Description
The latch is ideally suited for use as temporary stage for binary information processing and input/output
units. When either
S
or
R
is low, output is dependent on
R
input. When both inputs are high, Output is
stored before the indicated steady-state input conditions were established. And when both inputs are low,
output is high, but this high level are uncontinuance, if either of input goes high.
Features
鈥?/div>
High Speed Operation: t
pd
(S to Q) = 10 ns typ (C
L
= 50 pF)
鈥?/div>
High Output Current: Fanout of 10 LSTTL Loads
鈥?/div>
Wide Operating Voltage: V
CC
= 2 to 6 V
鈥?/div>
Low Input Current: 1 碌A(chǔ) max
鈥?/div>
Low Quiescent Supply Current: I
CC
(static) = 2 碌A(chǔ) max (Ta = 25擄C)
Function Table
Input
S*
2
H
L
H
L
H :
L :
Q
0
:
Notes:
R
H
H
L
L
Output
Q
Q
0
H
L
H*
1
High level
Low level
The level of Q respectively, before the indicated steady-state input conditions were established.
1. It is unpredictable, if
S
or
R
goes High.
2. As to latches which has two
S
inputs.
H: Both of
S
inputs are high.
L: Either or both of
S
inputs are low.

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