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HD74HC166 Datasheet

  • HD74HC166

  • Parallel-load 8-bit Shift Register

  • 60.22KB

  • 10頁

  • HITACHI

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HD74HC166
Parallel-load 8-bit Shift Register
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register
either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in
parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock
inhibit or Clock. Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating
one of the clock inputs to act as a clock inhibit.
Features
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High Speed Operation: t
pd
(Clock to Q
H
) = 14 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 碌A max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A max (Ta = 25擄C)
Function Table
Inputs
Parallel
Clear
L
H
H
H
H
H
Shift/Load
X
X
L
H
H
X
Clock Inhibit
X
L
L
L
L
H
Clock
X
L
Serial
X
X
X
H
L
X
A 路路路 H
X
X
a 路路路 h
X
X
X
Internal Outputs
Q
A
L
Q
A0
a
H
L
Q
A0
Q
B
L
Q
B0
b
Q
An
Q
An
Q
B0
Output
Q
H
L
Q
H0
h
Q
Gn
Q
Gn
Q
H0

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