HD74HC155
Dual 2-to-4-line Decoders/Demultiplexers
Description
This circuit features dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address
input. When both sections are enabled by the strobes, the common binary-address inputs sequentially
select and route associated input data to the appropriate output of each section. The individual strobes
permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted
through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-
line demultiplexer without external gating.
Features
鈥?/div>
High Speed Operation: t
pd
(A or B to Y) = 15 ns typ (C
L
= 50 pF)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1 碌A(chǔ) max
Low Quiescent Supply Current: I
CC
(static) = 4 碌A(chǔ) max (Ta = 25擄C)
Function Table
2-line-to-4-line Decoder/1-line-to-4-line Demultiplexer
Inputs
Select
B
X
L
L
H
H
X
A
X
L
H
L
H
X
Strobe
1G
H
L
L
L
L
X
Data
1C
X
H
H
H
H
L
Outputs
1Y
0
H
L
H
H
H
H
1Y
1
H
H
L
H
H
H
1Y
2
H
H
H
L
H
H
1Y
3
H
H
H
H
L
H
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