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HD74ALVC16834 Datasheet

  • HD74ALVC16834

  • 18-bit Universal Bus Driver with 3-state Outputs and Inverte...

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HD74ALVC16834
18-bit Universal Bus Driver with 3-state Outputs
and Inverted Latch Enable
ADE-205-216D (Z)
5th. Edition
December 1999
Description
The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode
when the latch enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or
low logic level. If
LE
is high, the A data is stored in the latch/flip flop on the low to high transition of the
CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
Features
鈥?/div>
Meets 鈥淧C SDRAM registered DIMM design support document, Rev. 1.2鈥?/div>
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current
鹵24
mA (@V
CC
= 3.0 V)

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