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HD74ALVC162834ANEL Datasheet

  • HD74ALVC162834ANEL

  • Buffer/Driver

  • 91.62KB

  • 17頁

  • ETC

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HD74ALVC162834A
18-bit Universal Bus Driver with 3-state Outputs
and Inverted Latch Enable
ADE-205-293B (Z)
Rev. 2
Oct. 2001
Description
The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V V
CC
operation.
Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode
when the latch enable (LE) is low. When
LE
is low, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If the
LE
is high, the A data is stored in the latch/flip flop on the low to high
transition of CLK. When
OE
is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver.
All outputs, which are designed to sink up to 12 mA, include series dumping resistors to reduce overshoot
and undershoot.
Features
鈥?/div>
Supports PC133 and meets 鈥淧C SDRAM registered DIMM specification, Rev. 1.1鈥?/div>
鈥?/div>
V
CC
= 2.3 V to 3.6 V
鈥?/div>
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
鈥?/div>
High output current 鹵12 mA (@V
CC
= 3.0 V)
鈥?/div>
All outputs have series dumping resistors, so no external resistors are required
鈥?/div>
t
pd
(CLK to Y) = 3.5 ns (Max) (@V
CC
= 3.3鹵0.3 V, C
L
= 50 pF, Ta = 0 to 85擄C)
鈥?/div>
t
pd
(CLK to Y) = 2.5 ns (Max) (@V
CC
= 3.3鹵0.3 V, C
L
= 30 pF, Ta = 0 to 85擄C)
鈥?/div>
Package type
Package type
TSSOP-56pin
TVSOP-56pin
Package code
TTP-56DAV
TTP-56DBV
Package suffix
T
N
Taping code
EL(1000pcs / Reel)
EL(1000pcs / Reel)

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