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HD74ACT298T Datasheet

  • HD74ACT298T

  • LOGIC MUX|QUAD|2-INPUT|ACT-CMOS|TSSOP|20PIN|PLASTIC

  • 54.95KB

  • 12頁

  • ETC

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HD74ALVCH16832
1-to-4 Address Register / Driver with 3-state Outputs
ADE-205-214B (Z)
3rd. Edition
January 2001
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V V
CC
operation.
The device is ideal for use in applications in which a single address bus is driving four separate memory
locations. The HD74ALVCH16832 can be used as a buffer or a register, depending on the logic level of
the select (SEL) input.
When
SEL
is a logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) inputs. Each
OE
controls two groups of seven outputs.
When
SEL
is a logic low, the device is in the register mode. The register is an edge triggered D-type flip
flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal
registers.
OE
controls operate the same as in the buffer mode.
When
OE
is a logic low, the outputs are in a normal logic state (high or low logic level). When
OE
is a
logic high, the outputs are in the high impedance state.
Neither
SEL
nor
OE
affect the internal operation of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down,
OE
should be tied to V
CC
through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
V
CC
= 2.3 V to 3.6 V
Typical V
OL
ground bounce < 0.8 V (@V
CC
= 3.3 V, Ta = 25擄C)
Typical V
OH
undershoot > 2.0 V (@V
CC
= 3.3 V, Ta = 25擄C)
High output current
鹵24
mA (@V
CC
= 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

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