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HD74AC273P Datasheet

  • HD74AC273P

  • Octal D-Type Flip-Flop

  • 10頁

  • ETC

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HD74AC273
Octal D Flip-Flop
Description
The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High
clock transition, is transferred to the corresponding flip-flops鈥檚 Q output
All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the
MR
input. The device is useful for applications where the true output only is required and the Clock and Master
Reset are common to all storage elements.
Features
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Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip-Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See HD74AC373 for Transparent Latch Version
See HD74AC374 for 3-State Version
Outputs Source/Sink 24 mA

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