HCS74MS
September 1995
Radiation Hardened Dual-D
Flip-Flop with Set and Reset
Pinouts
14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T14, LEAD FINISH C
TOP VIEW
R1N 1
D1 2
CP1 3
S1N 4
Q1 5
Q1N 6
GND 7
14 VCC
13 R2N
12 D2
11 CP2
10 S2N
9 Q2
8 Q2N
Features
鈥?3 Micron Radiation Hardened SOS CMOS
鈥?Total Dose 200K RAD (Si)
鈥?SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
鈥?Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
鈥?Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
鈥?Dose Rate Upset >10
10
RAD (Si)/s 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range: -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A(chǔ) at VOL, VOH
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
R1
D1
CP1
S1
Q1
Q1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
R2
D2
CP2
S2
Q2
Q2
Description
The Intersil HCS74MS is a Radiation Hardened positive
edge triggered 鏗俰p-鏗俹p with set and reset.
The HCS74MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS74MS is supplied in a 14 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
Ordering Information
PART NUMBER
HCS74DMSR
HCS74KMSR
HCS74D/Sample
HCS74K/Sample
HCS74HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
+25
o
C
+25
o
C
+25
o
C
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
14 Lead SBDIP
14 Lead Ceramic Flatpack
14 Lead SBDIP
14 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
File Number
83
518772
2142.2
next