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HCS166HMSR Datasheet

  • HCS166HMSR

  • Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift ...

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  • INTERSIL   INTERSIL

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HCS166MS
September 1995
Radiation Hardened 8-Bit
Parallel-Input/Serial Output Shift Register
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
DS
D0
D1
D2
D3
CE
CP
GND
1
2
3
4
5
6
7
8
16 VCC
15 PE
14 D7
13 Q7
12 D6
11 D5
10 D4
9 MR
Features
鈥?3 Micron Radiation Hardened CMOS SOS
鈥?Total Dose 200K RAD (Si)
鈥?SEP Effective LET No Upsets: >100 MEV-cm
2
/mg
鈥?Single Event Upset (SEU) Immunity < 2 x 10
-9
Errors/
Bit-Day (Typ)
鈥?Dose Rate Survivability: >1 x 10
12
RAD (Si)/s
鈥?Dose Rate Upset >10
10
RAD s(Si)/s 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Fanout (Over Temperature Range)
- Standard Outputs - 10 LSTTL Loads
鈥?Military Temperature Range: -55
o
C
to
+125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL ICs
鈥?DC Operating Voltage Range: 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 0.3 VCC Max
- VIH = 0.7 VCC Min
鈥?Input Current Levels Ii
鈮?/div>
5碌A(chǔ) at VOL, VOH
16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
DS
D0
D1
D2
D3
CE
CP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
PE
D7
Q7
D6
D5
D4
MR
Description
The Intersil HCS166MS is an 8-bit shift register that has fully
synchronous serial or parallel data entry selected by an
active LOW Parallel Enable (PE) input. When the PE is LOW
one setup time before the LOW-to-HIGH clock transition,
parallel data is entered into the register. When PE is HIGH,
data is entered into internal bit position Q0 from Serial Data
Input (DS), and the remaining bits are shifted one place to
the right (Q0
鈫?/div>
Q1
鈫?/div>
Q2m etc.) with each positive-going
clock transition. For expansion of the register in parallel to
serial converters, the Q7 output is connected to the DS input
of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
con be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
The HCS166MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS166MS is supplied in a 16 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
Ordering Information
PART
NUMBER
HCS166DMSR
TEMPERATURE
RANGE
SCREENING
LEVEL
PACKAGE
-55
o
C to +125
o
C Intersil Class S 16 Lead
Equivalent
SBDIP
-55
o
C to +125
o
C Intersil Class S 16 Lead
Equivalent
Ceramic
Flatpack
+25
o
C
Sample
16 Lead
SBDIP
16 Lead
Ceramic
Flatpack
Die
HCS166KMSR
HCS166D/
Sample
HCS166K/
Sample
+25
o
C
Sample
HCS166HMSR
+25
o
C
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
File Number
250
518758
2482.2

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