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Description
The Intersil HCS125MS is a Radiation Hardened quad three-state
buffer, each having its own output enable input. A high level on the
enable input puts the output in a high impedance state.
The HCS125MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family.
The HCS125MS is supplied in a 14 lead Ceramic 鏗俛tpack
(K suf鏗亁) or a SBDIP Package (D suf鏗亁).
OE1
A1
Y1
OE2
A2
Y2
GND
14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP3-F14, LEAD FINISH C
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
OE4
A4
Y4
OE3
A3
Y3
Ordering Information
PART
NUMBER
HCS125DMSR
TEMPERATURE
RANGE
-55
o
C
to
+125
o
C
SCREENING
LEVEL
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
PACKAGE
Functional Diagram
An
P
n
Yn
14 Lead SBDIP
OEn
HCS125KMSR
-55
o
C
to
+125
o
C
14 Lead Ceramic
Flatpack
14 Lead SBDIP
TRUTH TABLE
INPUTS
An
H
L
X
OEn
L
L
H
OUTPUT
Yn
H
L
Z
HCS125D/
Sample
HCS125K/
Sample
HCS125HMSR
+25
o
C
+25
o
C
Sample
14 Lead Ceramic
Flatpack
Die
+25
o
C
Die
L = Low, H = High, X = Don鈥檛 Care, Z = High Impedance
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
File Number
123
518831
3559.1