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HCF4033BEY Datasheet

  • HCF4033BEY

  • DECADE COUNTER/DIVIDER WITH DECODED 7-SEGMENT DISPLAY OUTPUT...

  • 604.44KB

  • 11頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCF4033B
DECADE COUNTER/DIVIDER WITH DECODED
7-SEGMENT DISPLAY OUTPUT AND RIPPLE BLANKING
s
s
s
s
s
s
s
s
s
s
COUNTER AND 7-SEGMENT DECODING IN
ONE PACKAGE
EASILY INTERFACED WITH 7-SEGMENT
DISPLAY TYPES
FULLY STATIC COUNTER OPERATION : DC
TO 6MHz (Typ.) AT V
DD
= 10V
IDEAL FOR LOW POWER DISPLAYS
RIPPLE BLANKING AND LAMP TEST
QUIESCENT CURRENT SPECIF. UP TO 20V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
INPUT LEAKAGE CURRENT
I
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25擄C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DIP
SOP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF4033BEY
HCF4033BM1
T&R
HCF4033M013TR
DESCRIPTION
The HCF4033B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4033B consists of a 5-stages Johnson
decade counter and an output decoder which
converts the Johnson code to a 7 segment
decoded output for driving one stage in a
numerical display. This device is particularly
advantageous in display applications where low
power dissipation and/or low package count are
PIN CONNECTION
important. This device has CLOCK, RESET,
CLOCK INHIBIT, RIPPLE BLANKING, LAMP
TEST input, CARRY OUT, RIPPLE BLANKING
and 7 DECODED outputs (a to g).
A high RESET signal clears the decade counter to
its zero count. The counter is advanced one count
at the positive clock signal transition if the CLOCK
INHIBIT signal is low. Counter advancement via
the clock line is inhibited when the CLOCK
INHIBIT signal is high. Antilock gating is provided
on the JOHNSON counter, thus assuring proper
counting sequence. The CARRY-OUT (C
OUT
)
signal completes one cycle every ten CLOCK
INPUT cycles and is used to clock the succeeding
decade directly in a multi-decade counting chain.
September 2001
1/11

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