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HCF4031BC1 Datasheet

  • HCF4031BC1

  • 64-STAGE STATIC SHIFT REGISTER

  • 243.47KB

  • 12頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF4031B
64-STAGE STATIC SHIFT REGISTER
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FULLY STATIC OPERATION : DC to 16MHz
(TYP.) @ V
DD
鈥?V
SS
= 15V
STANDARD TTL DRIVE CAPABILITY ON Q
OUTPUT
RECIRCULATION CAPABILITY
THREE CASCADING MODES :
DIRECT CLOCKING FOR HIGH-SPEED
OPERATION
DELAYED CLOCKING FOR REDUCED CLOCK
DRIVE REQUIREMENTS
ADDITIONAL 1/2 STAGE FOR SLOW CLOCKS
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA at 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N
O
. 13A, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4031BF
HCF4031BEY
HCF4031BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4031B
(extended temperature range) and
HCF4031B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The
HCC/HCF4031B
is a static shift register that
contains 64 D-type, master-slave flip-flop stages
and one stage which is a D-type master flip-flop only
(referred to as a 1/2 stage). The logic level present
at the DATA input is transferred into the first stage
and shifted one stage at each positive-going clock
transition. Maximum clock frequencies up to 16
Megahertz (typical) can be obtained. Because fully
static operation is allowed, information can be per-
manently stored with the clock line in either the low
or high state. The
HCC/HCF4031B
has a MODE
CONTROL input that, when in the high state, allows
operation in the recirculating mode. The MODE
CONTROL input can also be used to select between
two separate data sources. Register packages can
be cascaded and the clock lines driven directly for
high-speed operation. Alternatively, a delayed clock
output(CL
D
) is provided that enables cascading reg-
June 1989
1/12

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