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HCF40108BC1 Datasheet

  • HCF40108BC1

  • 4 x 4 MULTIPORT REGISTER

  • 14頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC40108B
HCF40108B
4 x 4 MULTIPORT REGISTER
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FOUR 4-BIT REGISTERS
ONE INPUT AND TWO OUTPUT BUSES
UNLIMITED EXPANSION IN BIT AND WORD
DIRECTION
DATA LINES HAVE LATCHED INPUTS
3-STATE OUTPUTS
SEPARATE CONTROL OF EACH BUS,
ALLOWING SIMULTANEOUS INDEPENDET
READING AND ANY OF FOUR REGISTERS
ON BUS A AND BUS B AND INDEPENDENT
WRITING INTO ANY ANY OF THE FOUR REG-
ISTERS
40108B IS PIN COMPATIBLE WITH INDUSTRY
TYPE MC14580
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
5V, 10V AND 15V PARAMETRIC RATINGS
INPUT CURRENTOF 100 nA AT 18V AND 25oC
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD No 13a, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF B
SERIES CMOS DEVICES鈥?/div>
no new data is netered. In either case, the contents
of any word may be accessed via the read address
lines independent of the state of the CLOCK input.
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC40108BF
HCF40108BM1
HCF40108BEY
HCF40108BC1
PIN CONNECTIONS
DESCRIPTION
The HCC40108B (extended temperature range)
and HCF40108B (intermediate temperature range)
are monolithic integrated circuits, available in 24
lead dual in line plastic or ceramic packageand plas-
tic micropackage. The HCC/HCF40108B is a 4 X 4
multiport register containing four 4-bit register, write
address decoder, two separate read address
decoders, and two 3-state output buses. When the
ENABLE input is low, the corresponding output bus
is switched, independently of the clock, to a high im-
pedance state. The high impedance third state pro-
vides the outputs with the capability of being
connected to the bus lines in a bus organized sys-
tem without the need for interface or pull-up compo-
nents. When the WRITE ENABLE input is high, all
data input lines are latched on the positive transition
of the CLOCK and the data is entered into the word
selected by the write address lines. When WRITE
ENABLE is low, the CLOCK is inhibited and
September 1988
1/14

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