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HCC4517BF Datasheet

  • HCC4517BF

  • DUAL 64-STAGE STATIC SHIFT REGISTER

  • 12頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF4517B
DUAL 64-STAGE STATIC SHIFT REGISTER
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CLOCK FREQUENCY 12MHz (TYP.) AT V
DD
=
10V
SCHMITT TRIGGER CLOCK INPUTS ALLOW
OPERATION WITH VERY SLOW CLOCK RISE
AND FALL TIMES
THREE-STATE OUTPUTS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURREN OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N擄. 13A, 鈥漇TANDARD
SPECIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
(Plastic Package)
F
(Ceramic Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4517BF
HCF4517BM1
HCF4517BC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4517B
(extended temperature range) and
HCF4517B
(intermediate temperature range) are
monolithic integrated circuits, available in 16-lead
dual in-line plastic or ceramic package.
The
HCC/HCF4517B
dual 64-stage static shift reg-
ister consists of two independent registers each
having a clock, data, and write enable input and out-
puts accessible at taps following the 16th, 32nd,
48th, and 64th stages. These taps also serve as
input points allowing data to be inputted at the 17th,
33rd, and 49th stages when the write enable input
is a logic 1 and the clock goes through a low-to-high
transition. The truth table indicates how the clock
and write enable inputs control the operation of the
HCC/HCF4517B.
Inputs at the intermediate taps
allow entry of 64 bits into the register with 16 clock
pulses. The 3-state outputs permit connection of this
device to an external bus.
September 1988
1/12

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