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HCC4033BM1 Datasheet

  • HCC4033BM1

  • 7-SEGMENT DISPLAY OUTPUTS DECADE COUNTERS/DIVIDERS WITH DECO...

  • 15頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF4026B
HCC/HCF4033B
DECADE COUNTERS/DIVIDERS WITH DECODED
7-SEGMENT DISPLAY OUTPUTS
.
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.
.
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WITH; DISPLAY ENABLE 4026B
RIPPLE BLANKING 4033B
COUNTER AND 7-SEGMENT DECODING IN
ONE PACKAGE
EASILY INTERFACED WITH 7-SEGMENT DIS-
PLAY TYPES
FULLY STATIC COUNTER OPERATION : DC
TO 6MHz (typ.) AT V
DD
= 10V
IDEAL FOR LOW-POWER DISPLAYS
DISPLAY ENABLE OUTPUT - 4026B
鈥漅IPPLE BLANKING鈥?AND LAMP TEST - 4033B
QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
5V, 10V, AND 15V PARAMETRIC RATING
INPUT CURRENT OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N擄 13A, 鈥漇TANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
EY
(Plastic Package)
F
(Ceramic Frit Seal Package)
M1
(Micro Package)
C1
(Plastic Chip Carrier)
ORDER CODES :
HCC40XXBF
HCF40XXBM1
HCF40XXBEY
HCF40XXBC1
PIN CONNECTIONS
DESCRIPTION
The
HCC4026B/4033B
(extended temperature
range) and
HCF4026B/4033B
(intermediate tem-
perature range) are monolithic integrated circuits,
available in 16-lead dual in-line plastic or ceramic
package and plastic micro package. The
HCC/HCF4026B
and
HCC/HCF4033B
each con-
sist of a 5-stage Johnson decade counter and an
output decoder which converts the Johnson code to
a 7-segment decoded output for driving one stage
in a numerical display. These devices are particu-
larly advantageous in display applications where
low power dissipation and/or low package count are
important. Inputs common to both types are
CLOCK, RESET, & CLOCK INHIBIT ; common out-
puts are CARRY OUT and the seven decoded out-
puts (a, b, c, d, e, f, g). Additional inputs and outputs
for the
HCC/HCF4026B
include DISPLAY ENABLE
input and DISPLAY ENABLE and UNGATED 鈥滳-
SEGMENT鈥?outputs. Signals peculiar to the
HCC/HCF4033B
are RIPPLE-BLANKING INPUT
AND LAMP TEST INPUT and a RIPPLE-BLANK-
ING OUTPUT. A high RESET signal clears the de-
June 1989
4026B
4033B
1/15

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