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HCC40208BF Datasheet

  • HCC40208BF

  • 4 x 4 MULTIPORT REGISTER

  • 13頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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HCC/HCF40208B
4 x 4 MULTIPORT REGISTER
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FOUR 4-BIT REGISTERS
ONE INPUT AND TWO OUTPUT BUSES
UNLIMITED EXPANSION IN BIT AND WORD
DIRECTIONS
DATA LINES HAVE LATCHED INPUTS
3-STATE OUTPUTS
SEPARATE CONTROL OF EACH BUS,
ALLOWING SIMULTANEOUS INDEPENDENT
READING OF ANY OF FOUR REGISTERS ON
BUS A AND BUS B AND INDEPENDENT WRIT-
ING INTO ANY OF THE FOUR REGISTERS
40108B IS PIN-COMPATIBLE WITH INDUS-
TRY TYPE MC14580
STANDARDIZED, SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED AT 20V
FOR HCC DEVICE
5V, 10V, AND 15V PARAMETRIC RATINGS
INPUT CURRENT OF 100nA AT 18V AND 25擄C
FOR HCC DEVICE
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC TEN-
TATIVE STANDARD N擄 13A, 鈥漇TANDARD SPE-
CIFICATIONS FOR DESCRIPTION OF 鈥滲鈥?/div>
SERIES CMOS DEVICES鈥?/div>
BEY
(Plastic Package)
BF
(Ceramic Frit Seal Package)
BM1
(Micro Package)
ORDER CODES :
HCC40208BF
HCF40208BEY
HCF40208BM1
PIN CONNECTIONS
DESCRIPTION
The
HCC40208B
(extended temperature range) and
HCF40208B
(intermediate temperature range) are
monolithic integrated circuits, available in 24-lead dual
in-line plastic or ceramic package and plastic micro
package. The
HCC/HCF40208B
is a 4 x 4 multiport
register containing four 4-bit registers, write address
decoder, two separate read address decoders, and
two 3-state output buses. When the ENABLE input is
low, the corresponding output bus is switched, inde-
pendently of the clock to a high-impedance state. The
high-impedance third state provides the outputs with
the capability of being connected to the bus lines in a
bus-organized system without the need for interface or
pull-up components. When the WRITE ENABLE input
is high, all data input lines are latched on the positive
transition of the CLOCKand the data is entered into the
wordselected bythewrite address lines. When WRITE
ENABLE is low, the CLOCK is inhibited and no new
data is entered. In either case, the contents of any word
may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
June 1989
1/13

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