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HB54R1G9F2-A75B Datasheet

  • HB54R1G9F2-A75B

  • 1GB Registered DDR SDRAM DIMM

  • 16頁(yè)

  • ELPIDA

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DATA SHEET
1GB Registered DDR SDRAM DIMM
HB54R1G9F2-A75B/B75B/10B (128M words
脳
72 bits, 2 Banks)
Description
The HB54R1G9F2 is a 128M
脳
72
脳
2 bank Double
Data Rate (DDR) SDRAM Module, mounted 36 pieces
of 256Mbits DDR SDRAM (HM5425401BTB) sealed in
TCP package, 1 piece of PLL clock driver, 2 pieces of
register driver and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD). Read and write
operations are performed at the cross points of the CK
and the /CK. This high-speed data transfer is realized
by the 2-bit prefetch-pipelined architecture. Data
strobe (DQS) both for read and write are available for
high speed and reliable data bus design. By setting
extended mode register, the on-chip Delay Locked
Loop (DLL) can be set enable or disable. An outline of
the products is 184-pin socket type package (dual lead
out). Therefore, it makes high density mounting
possible without surface mount technology. It provides
common data inputs and outputs.
Decoupling
capacitors are mounted beside each TCP on the
module board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
鈥?/div>
184-pin socket type package (dual lead out)
錚?/div>
Outline: 133.35mm (Length)
脳
43.18mm (Height)
脳
4.80mm (Thickness)
錚?/div>
Lead pitch: 1.27mm
鈥?/div>
2.5V power supply (VCC/VCCQ)
鈥?/div>
SSTL-2 interface for all inputs and outputs
鈥?/div>
Clock frequency: 143MHz/133MHz/125MHz (max.)
鈥?/div>
Data inputs and outputs are synchronized with DQS
鈥?/div>
4 banks can operate simultaneously and
independently (Component)
鈥?/div>
Burst read/write operation
鈥?/div>
Programmable burst length: 2, 4, 8
錚?/div>
Burst read stop capability
鈥?/div>
Programmable burst sequence
錚?/div>
Sequential
錚?/div>
Interleave
鈥?/div>
Start addressing capability
錚?/div>
Even and Odd
鈥?/div>
Programmable /CAS latency (CL): 3, 3.5
鈥?/div>
8192 refresh cycles: 7.8碌s (8192/64ms)
鈥?/div>
2 variations of refresh
錚?/div>
Auto refresh
錚?/div>
Self refresh
Document No. E0089H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
錚〦lpida
Memory, Inc. 2001-2002
錚〩itachi,
Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

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