DATA SHEET
512MB Unbuffered SDRAM S.O.DIMM
HB52RF649DC-B (64M words
脳
72 bits, 2 bank)
HB52RD649DC-B (64M words
脳
72 bits, 2 bank)
Description
The HB52RF649DC, HB52RD649DC are a 64M
脳
72
脳
2 banks Synchronous Dynamic RAM Small Outline
Dual In-line Memory Module (S.O.DIMM), mounted 18
pieces of 256M bits SDRAM sealed in TCP package
and 1 piece of serial EEPROM (2k bits) for Presence
Detect (PD). An outline of the products is 144-pin Zig
Zag Dual tabs socket type compact and thin package.
Therefore, they make high density mounting possible
without surface mount technology.
They provide
common data inputs and outputs.
Decoupling
capacitors are mounted beside TCP on the module
board.
Note: Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
鈥?/div>
Fully compatible with: JEDEC standard outline 8
bytes S.O.DIMM
鈥?/div>
144-pin Zig Zag Dual tabs socket type (dual lead out)
錚?/div>
PCB height: 33.02mm (1.30inch)
錚?/div>
Lead pitch: 0.80mm
鈥?/div>
3.3V power supply
鈥?/div>
Clock frequency: 133MHz/100MHz (max.)
鈥?/div>
LVTTL interface
鈥?/div>
Data bus width:
脳
72 ECC
鈥?/div>
Single pulsed /RAS
鈥?/div>
4 Banks can operates simultaneously and
independently
鈥?/div>
Burst read/write operation and burst read/single write
operation capability
鈥?/div>
Programmable burst length (BL): 1, 2, 4, 8
鈥?/div>
2 variations of burst sequence
錚?/div>
Sequential
錚?/div>
Interleave
鈥?/div>
Programmable /CE latency (CL): 2, 3
鈥?/div>
Byte control by DQMB
鈥?/div>
Refresh cycles: 8192 refresh cycles/64ms
鈥?/div>
2 variations of refresh
錚?/div>
Auto refresh
錚?/div>
Self refresh
鈥?/div>
Low self refresh current
: HB52RF649DC-xxBL (L-version)
: HB52RD649DC-xxBL (L-version)
Document No. E0223H30 (Ver. 3.0)
Date Published April 2002 (K) Japan
URL: http://www.elpida.com
錚〦lpida
Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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