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GVT73128S16T-15 Datasheet

  • GVT73128S16T-15

  • x16 SRAM

  • 11頁

  • ETC

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GALVANTECH
, INC.
ASYNCHRONOUS
SRAM
FEATURES
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GVT73128S16
REVOLUTIONARY PINOUT 64K X 16 X 2
64K x 16 x 2 SRAM
+3.3V SUPPLY, TWO CHIP ENABLES
REVOLUTIONARY PINOUT
GENERAL DESCRIPTIO N
The GVT73128S16 is organized as a 65,536 x 16 x 2
SRAM using a four-transistor memory cell with a high
performance, silicon gate, low-power CMOS process.
Galvantech SRAMs are fabricated using triple-layer
polysilicon, double-layer metal technology.
This device consists of two banks of 64K x 16 memory.
Each bank of memory has its own chip enable pin and the
highest order address. Memory bank A has CEA# and A15A
as its chip enable and high order address. Memory bank B has
CEB# and A15B as its chip enable and high order address.
The other low order addresses (A0 to A14) along with the
write enable (WE#) and output enable (OE#) are shared by
both memory banks.
This device offers center power and ground pins for
improved performance and noise immunity. Static design
eliminates the need for external clocks or timing strobes. For
increased system flexibility and eliminating bus contention
problems, this device offers chip enables (CEA# and CEB#)
and output enable (OE#) with this organization.
Writing to these devices is accomplished when write
enable (WE#) and chip enables (CEA# and/or CEB#) inputs
are both LOW. Reading is accomplished when (CEA# or
CEB#) and (OE#) go LOW with (WE#) remaining HIGH.
The device offers a low power standby mode when both
banks of memory are not selected. This allows system
designers to meet low standby power requirements.
Fast access times: 10, 12, and 15ns
Fast OE# access times: 5, 6, and 7ns
Single +3.3V +0.3V power supply
Fully static -- no clock or timing strobes necessary
All inputs and outputs are TTL-compatible
Three state outputs
Center power and ground pins for greater noise immunity
Easy memory expansion with CE# and OE# options
Automatic CE# power down
High-performance, low-power consumption, CMOS
triple-poly, double-metal process
Packaged in 44-pin, 400-mil TSOP and 44-pin TQFP
OPTIONS
Timing
10ns access
12ns access
15ns access
Packages
44-pin TSOP (400 mil)
44-pin TQFP
Power consumption
Standard
Temperature
Commercial
MARKING
-10
-12
-15
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Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site: http://www.galvantech.com
Rev. 1/99
Galvantech, Inc. reserves the right to chang
e
products or specifications without notice
.

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