GTLP6C816A LVTTL-to-GTLP Clock Driver
August 1998
Revised August 1999
GTLP6C816A
LVTTL-to-GTLP Clock Driver
General Description
The GTLP6C816A is a clock driver that provides LVTTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTL(P)鈥檚 reduced output swing (<1V), reduced
input threshold levels and output edge rate control. The
edge rate control minimizes bus settling time. GTLP is a
Fairchild Semiconductor derivative of the Gunning Trans-
ceiver logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Interface between LVTTL and GTLP logic levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down high impedance for live insertion
s
1:6 fanout clock driver for LVTTL port
s
1:2 fanout clock driver for GTLP port
s
LVTTL compatible driver and control inputs
s
Flow through pinout optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A Port source/sink
鈭?4/+24
mA
s
B Port sink 50 mA
s
鈭?0擄C
to
+85擄C
temperature capability
s
Low voltage version of GTLP6C816
Ordering Code:
Order Number
GTLP6C816AMTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Descriptions
Pin Names
Description
TTLIN, GTLPIN Clock Inputs
(LVTTL and GTLP respectively)
OEB
OEA
V
CCT
.GNDT
V
CC
GNDG
V
REF
OA0鈥揙A5
OB0鈥揙B1
Output Enable (Active LOW)
GTLP Port (LVTTL Levels)
Output Enable (Active LOW)
TTL Port (LVTTL Levels)
TTL Output Supplies
Internal Circuitry V
CC
OBn GTLP Output Grounds
Voltage Reference Input
TTL Buffered Clock Outputs
GTLP Buffered Clock Outputs
Connection Diagram
漏 1999 Fairchild Semiconductor Corporation
DS500179
www.fairchildsemi.com
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