GTLP2T152 2-Bit LVTTL/GTLP Transceiver
June 2001
Revised February 2002
GTLP2T152
2-Bit LVTTL/GTLP Transceiver
General Description
The GTLP2T152 is a 2-bit transceiver that provides LVTTL-
to-GTLP signal level translation. Data directional control is
handled with a transmit/receive pin. High-speed backplane
operation is a direct result of GTLP鈥檚 reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus-settling time.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage and temperature compensated. GTLP鈥檚 I/O
structure is similar to GTL and BTL but offers different out-
put levels and receiver threshold. Typical GTLP output volt-
age levels are: V
OL
=
0.5V, V
OH
=
1.5V, and V
REF
=
1V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP2T152M
GTLP2T152MX
GTLP2T152K8X
Package Number Package Description
M08A
M08A
MAB08A
(Preliminary)
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
Pin Descriptions
Pin Names
T/R
Description
LVTTL Direction Control
(Receive Direction is Active LOW)
Connection Diagrams
US8
V
CC
, GND, V
REF
Device Supplies
A
n
B
n
A Port LVTTL Input/Output
B Port GTLP Input/Output
SOIC
漏 2002 Fairchild Semiconductor Corporation
DS500486
www.fairchildsemi.com
1
2
3
4
5
6
7
