音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GTLP17T616MTD Datasheet

  • GTLP17T616MTD

  • 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock

  • 10頁

  • FAIRCHILD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
January 2000
Revised February 2000
GTLP17T616
17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock
General Description
The GTLP17T616 is a 17-bit registered bus transceiver
that provides LVTTL to GTLP signal level translation. It
allows for transparent, latched and clocked modes of data
flow and provides a buffered GTLP (CLKOUT) clock output
from the LVTTL CLKAB. The device provides a high speed
interface between cards operating at LVTTL logic levels
and a backplane operating at GTLP logic levels. High
speed backplane operation is a direct result of GTLP鈥檚
reduced output swing (<1V), reduced input threshold levels
and output edge rate control. The edge rate control mini-
mizes bus settling time. GTLP is a Fairchild Semiconductor
derivative of the Gunning Transistor logic (GTL) JEDEC
standard JESD8-3.
Fairchild's GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different output
levels and receiver thresholds. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down high impedance for live insertion
s
External V
REF
pin for receiver threshold adjustability
s
BiCMOS technology for low power dissipation
s
Bushold data inputs on A Port eliminates the need for
external pull-up resistors for unused inputs
s
LVTTL compatible Driver and Control inputs
s
Flow-through architecture optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A Port source/sink
鈭?4
mA/+24 mA
s
B Port sink capability +50 mA
s
D-type flip-flop, latch and transparent data paths
s
GTLP Buffered CLKAB signal available (CLKOUT)
s
鈭?0擄C
to
+85擄C
Temperature operation
Ordering Code:
Order Number
GTLP17T616MEA
GTLP17T616MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 2000 Fairchild Semiconductor Corporation
DS500327
www.fairchildsemi.com

GTLP17T616MTD 產(chǎn)品屬性

  • Fairchild Semiconductor

  • 總線收發(fā)器

  • CMOS

  • GTLP

  • 17

  • LVTTL, TTL

  • GTLP

  • 3-State

  • - 24 mA

  • 50 mA

  • 4.6 ns

  • 3.45 V

  • 3.15 V

  • + 85 C

  • TSSOP-56

  • Tube

  • 17-Bit Bus Transceiver with Voltage Translation

  • - 40 C

  • SMD/SMT

  • 1

  • Non-Inverting

  • 34

GTLP17T616MTD相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！