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GTLP16616 Datasheet

  • GTLP16616

  • 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock

  • 10頁(yè)

  • FAIRCHILD

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GTLP16616 17-Bit TTL/GTLP Bus Transceiver with Buffered Clock
June 1997
Revised October 1998
GTLP16616
17-B
it
TTL/GTLP Bus Transceiver
with Buffered Clock
General Description
The GTLP16616 is a 17-bit registered bus transceiver that
provides TTL to GTLP signal level translation. It allows for
transparent, latched and clocked modes of data flow and
provides a buffered GTLP (CLKOUT) clock output from the
TTL CLKAB. The device provides a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP鈥檚 reduced output
swing (<1V), reduced input threshold levels and output
edge rate control. The edge rate control minimizes bus set-
tling time. GTLP is a Fairchild Semiconductor derivative of
the Gunning Transceiver logic (GTL) JEDEC standard
JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and TTL logic
levels
s
Edge Rate Control to minimize noise on the GTLP port
s
Power up/down/off high impedance for live insertion
s
External V
REF
pin for receiver threshold
s
CMOS technology for low power dissipation
s
5 V tolerant inputs and outputs on the A-Port
s
Bus-hold data inputs on the A-Port eliminates the need
for external pull-up resistors on unused inputs.
s
TTL compatible driver and control inputs
s
Flow through pinout optimizes PCB layout
s
Open drain on GTLP to support wired-or connection
s
A-port source/sink
鈭?2
mA/+32 mA
s
D-type flip-flop, latch and transparent data paths
s
GTLP Buffered CLKAB signal available (CLKOUT)
s
Recommended Operating Temperature
鈭?0擄C
to 85擄C
Ordering Code:
Order Number
GTLP16616MEA
GTLP16616MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118 0.300鈥?Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 1998 Fairchild Semiconductor Corporation
DS500017.prf
www.fairchildsemi.com

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