GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
March 1995
Revised March 2001
GTLP16612
18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver
which provides TTL to GTLP signal level translation. The
device is designed to provide a high speed interface
between cards operating at TTL logic levels and a back-
plane operating at GTLP logic levels. High speed back-
plane operation is a direct result of GTLP鈥檚 reduced output
swing (
<
1V), reduced input threshold levels and output
edge rate control which minimizes signal settling times.
GTLP is a Fairchild Semiconductor derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is Pro-
cess, Voltage, and Temperature (PVT) compensated. Its
function is similar to BTL or GTL but with different driver
output levels and receiver threshold. GTLP output low volt-
age is typically less than 0.5V, the output high is 1.5V and
the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and TTL logic
levels
s
Designed with an edge rate control circuit to reduce
output noise on GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustability
s
Special PVT compensation circuitry to provide
consistent performance over variations of process,
supply voltage and temperature
s
TTL compatible Driver and Control inputs
s
Designed using Fairchild advanced CMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
5V tolerant inputs and outputs on LVTTL port
s
Open drain on GTLP to support wired-or connection
s
Flow-through pinout optimizes PCB layout
s
D-type flip-flop, latch and transparent data paths
s
A Port outputs source/sink
鈭?/div>
32 mA/
+
32 mA
Ordering Code:
Order Number
GTLP16612MEA
GTLP16612MTD
Package Number
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
漏 2001 Fairchild Semiconductor Corporation
DS012390
www.fairchildsemi.com
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