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GTLP10B320MTD Datasheet

  • GTLP10B320MTD

  • 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feed...

  • 12頁

  • FAIRCHILD

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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
May 2001
Revised May 2001
GTLP10B320
10-Bit LVTTL/GTLP Transceiver
with Split LVTTL Port and Feedback Path
General Description
The GTLP10B320 is a 10-bit Universal bus driver and
receiver, with separate LVTTL inputs and outputs and a
feedback path for diagnostics, that provides LVTTL to
GTLP signal level translation. High speed backplane oper-
ation is a direct result of GTLP鈥檚 reduced output swing
(
<
1V), reduced input threshold levels and output edge rate
control. The edge rate control minimizes bus settling time.
GTLP is a Fairchild Semiconductor derivative of the
Gunning Transistor logic (GTL) JEDEC standard JESD8-3.
Fairchild鈥檚 GTLP has internal edge-rate control and is pro-
cess, voltage and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output low level is typ-
ically less than 0.5V, the output level high is 1.5V and the
receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Variable edge rate control pin to select desired edge rate
on GTLP port (V
ERC
)
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Split LVTTL inputs and outputs
s
Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
A feedback path for control and diagnostics monitoring
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced BiCMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
鈭?/div>
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP10B320MTD
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2001 Fairchild Semiconductor Corporation
DS500483
www.fairchildsemi.com

GTLP10B320MTD 產(chǎn)品屬性

  • 34

  • 集成電路 (IC)

  • 邏輯 - 通用總線函數(shù)

  • 74GTLP

  • 通用總線驅動器

  • -

  • 10 位

  • 24mA，24mA

  • 3.15 V ~ 3.45 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 管件

GTLP10B320MTD相關型號PDF文件下載

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    2-Bit LVTTL/GTLP Transceiver
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    2-Bit LVTTL/GTLP Transceiver
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    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD
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    GTLP-to-TTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD
  • 英文版
    Low Drive GTLP-to-LVTTL 1:6 Clock Driver
    FAIRCHILD ...
  • 英文版
    8-Bit LVTTL/GTLP Bus Transceiver
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  • 英文版
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