GTL2014
4-bit LVTTL to GTL transceiver
Rev. 01 鈥?19 May 2005
Product data sheet
1. General description
The GTL2014 is a 4-bit translating transceiver designed for 3.3 V LVTTL system interface
with a GTL鈭?GTL/GTL+ bus.
The direction pin allows the part to function as either a GTL to LVTTL sampling receiver or
as a LVTTL to GTL interface.
The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs. The LVTTL outputs are not 5.5 V tolerant.
The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used
in higher voltage open-drain output applications.
2. Features
s
Operates as a 4-bit GTL鈭?GTL/GTL+ sampling receiver or as a LVTTL to
GTL鈭?GTL/GTL+ driver
s
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
s
GTL input and output 3.6 V tolerant
s
V
ref
adjustable from 0.5 V to V
CC
/2
s
Partial power-down permitted
s
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
s
Latch-up protection exceeds 500 mA per JESD78
s
Package offered: TSSOP14
3. Quick reference data
Table 1:
Quick reference data
T
amb
= 25
擄
C
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
C
i
C
io
input capacitance on pin DIR;
A-to-B or B-to-A
input/output capacitance; A-to-B
input/output capacitance; B-to-A
V
I
= 0 V or V
CC
outputs disabled;
V
I
and V
O
= 0 V or 3.0 V
propagation delay; Bn-to-An
C
L
= 50 pF; V
CC
= 3.3 V
Parameter
propagation delay; An-to-Bn
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
Min
-
-
-
-
-
-
-
Typ
2.8
3.4
5.2
4.9
2
4.6
3.4
Max
-
-
-
-
2.5
6.0
4.3
Unit
ns
ns
ns
ns
pF
pF
pF