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GT28F320W18TD80 Datasheet

  • GT28F320W18TD80

  • Intel㈢ Wireless Flash Memory

  • 100頁

  • INTEL   INTEL

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Intel
廬
Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
鈻?/div>
鈻?/div>
鈻?/div>
High Performance Read-While-Write/
Erase
鈥?Burst frequency at 66 MHz
鈥?60 ns Initial Access Read Speed
鈥?11 ns Burst-Mode Read Speed
鈥?20 ns Page-Mode Read Speed
鈥?4-, 8-, 16-, and Continuous-Word Burst
Mode Reads
鈥?Burst and Page Mode Reads in all
Blocks, across all partition boundaries
鈥?Burst Suspend Feature
鈥?Enhanced Factory Programming at
3.1 碌s/word (typ.for 0.13 碌m)
Security
鈥?128-bit Protection Register
鈥?64-bits Unique Programmed by Intel
鈥?64-bits User-Programmable
鈥?Absolute Write Protection with V
PP
at
Ground
鈥?Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
Capability
Quality and Reliability
鈥?Temperature Range: 鈥?0 擄C to +85 擄C
鈥?100k Erase Cycles per Block
鈥?0.13 碌m ETOX鈩?VIII Process
鈥?0.18 碌m ETOX鈩?VII Process
鈻?/div>
鈻?/div>
鈻?/div>
Architecture
鈥?Multiple 4-Mbit Partitions
鈥?Dual Operation: RWW or RWE
鈥?8KB parameter blocks
鈥?64KB main blocks
鈥?Top or Bottom Parameter Devices
鈥?16-bit wide data bus
Software
鈥?5 碌s (typ.) Program and Erase Suspend
Latency Time
鈥?Flash Data Integrator (FDI) and Common
Flash Interface (CFI) Compatible
鈥?Programmable WAIT Signal Polarity
Packaging and Power
鈥?0.13 碌m: 32-, 64-, and 128-Mbit in VF
BGA Package; 128-Mbit in QUAD+
Package
鈥?0.18 碌m: 32- and 128-Mbit Densities in
VF BGA Package; 64-Mbit Density in
碌BGA* Package
鈥?56 Active Ball Matrix, 0.75 mm Ball-
Pitch
鈥?V
CC
= 1.70 V to 1.95 V
鈥?V
CCQ
= 1.70 V to 2.24 V or 1.35 V to
1.80 V
鈥?Standby current (0.13 碌m): 8碌A(chǔ) (typ.)
鈥?Read current: 7mA (typ.)
The Intel
廬
Wireless Flash Memory (W18) device with flexible multi-partition dual operation,
provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for
low-voltage burst CPUs. Combining high read performance with flash memory鈥檚 intrinsic non-
volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing
redundant code memory from slow nonvolatile storage to faster execution memory. It reduces
the total memory requirement that increases reliability and reduces overall system power
consumption and cost.
The W18 device鈥檚 flexible multi-partition architecture allows programming or erasing to occur
in one partition while reading from another partition. This allows for higher data write
throughput compared to single partition architectures. The dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take
place in the background. The designer can also choose the size of the code and data partitions via
the flexible multi-partition architecture.
Notice:
This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
290701-009
December 2003

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