音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

GS881E36T-11 Datasheet

  • GS881E36T-11

  • 512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs

  • 469.09KB

  • 34頁

  • GSI

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預覽

Preliminary
GS881E18/36T-11/11.5/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
1.10 9/2000Features
鈥?FT pin for user-configurable flow through or pipelined
operation
鈥?Dual Cycle Deselect (DCD) operation
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?On-chip write parity checking; even or odd selectable
鈥?3.3 V +10%/鈥?% core power supply
鈥?2.5 V or 3.3 V I/O supply
鈥?LBO pin for Linear or Interleaved Burst mode
鈥?Internal input resistors on mode pins allow floating mode pins
鈥?Default to Interleaved Pipeline mode
鈥?Byte Write (BW) and/or Global Write (GW) operation
鈥?Common data inputs and data outputs
鈥?Clock Control, registered, address, data, and control
鈥?Internal self-timed write cycle
鈥?Automatic power-down for portable applications
鈥?100-lead TQFP package
-11
-11.5
-100
-80
-66
10 ns
10 ns 12.5 ns 15 ns
Pipeline tCycle 10 ns
4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns
3-1-1-1
t
KQ
I
DD
225 mA 225 mA 225 mA 200 mA 185 mA
11 ns 11.5 ns 12 ns
14 ns
18 ns
Flow
t
KQ
Through tCycle 15 ns
15 ns
15 ns
15 ns
20 ns
2-1-1-1
I
DD
180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 36 ByteSafe鈩?/div>
100 MHz鈥?6 MHz
3.3 V V
DD
8Mb Sync Burst SRAMs
3.3 V and 2.5 V I/O
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18//36T is a DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. SCD (Single Cycle Deselect)
versions are also available. DCD SRAMs pipeline disable
commands to the same degree as read commands. DCD RAMs
hold the deselect command for one full cycle and then begin
turning off their outputs just after the second rising edge of
clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
ByteSafe鈩?Parity Functions
Functional Description
Applications
The GS881E18//36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
The GS881E18/36T features ByteSafe data security functions.
See detailed discussion following.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18//36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
Rev: 1.10 9/2000
1/34
漏 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS881E36T-11相關型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    8Mb Sync Burst SRAMs
    ETC
  • 英文版
    512K x 18, 256K x 36 ByteSafe?? 8Mb Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    GSI Technology [512K x 18, 256K x 36 8Mb S/DCD Sync Burst S...
    GSI
  • 英文版
    512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    256K x 36 9Mb Sync Burst SRAM
    GSI [GSI T...
  • 英文版
    512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    GSI Technology [512K x 18, 256K x 36 8Mb Sync Burst SRAMs]
    GSI
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
    GSI
  • 英文版
    512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    9Mb Pipelined and Flow Through Synchronous NBT SRAM
    ETC
  • 英文版
    9Mb Pipelined and Flow Through Synchronous NBT SRAM
    ETC [ETC]
  • 英文版
    GSI Technology [8Mb Pipelined and Flow Through Synchronous ...
    GSI
  • 英文版
    GSI Technology [512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst...
    GSI
  • 英文版
    GSI Technology [256K x 36 9Mb Synchronous Burst SRAMs]
    GSI
  • 英文版
    256K x 36 9Mb SCD/DCD Sync Burst SRAM
    GSI [GSI Techno...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網(wǎng)站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！