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GS881E18BD-150IV Datasheet

  • GS881E18BD-150IV

  • 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs

  • 1524.66KB

  • 36頁

  • GSI

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GS881E18/32/36B(T/D)-xxxV
100-Pin TQFP & 165-bump BGA
Commercial Temp
Industrial Temp
Features
鈥?FT pin for user-configurable flow through or pipeline
operation
鈥?Dual Cycle Deselect (DCD) operation
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?1.8 V or 2.5 V +10%/鈥?0% core power supply
鈥?1.8 V or 2.5 V I/O supply
鈥?LBO pin for Linear or Interleaved Burst mode
鈥?Internal input resistors on mode pins allow floating mode pins
鈥?Default to Interleaved Pipeline mode
鈥?Byte Write (BW) and/or Global Write (GW) operation
鈥?Internal self-timed write cycle
鈥?Automatic power-down for portable applications
鈥?JEDEC-standard 100-lead TQFP and 165-bump BGA
packages
鈥?RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
512K x 18, 256K x 32, 256K x 36
9Mb Sync Burst SRAMs
250 MHz鈥?50 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
DCD Pipelined Reads
The GS881E18/32/36B(T/D)-xxxV is a DCD (Dual Cycle
Deselect) pipelined synchronous SRAM. SCD (Single Cycle
Deselect) versions are also available. DCD SRAMs pipeline
disable commands to the same degree as read commands. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge
of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS881E18/32/36B(T/D)-xxxV operates on a 1.8 V or 2.5
V power supply. All input are 2.5 V and 1.8 V compatible.
Separate output power (V
DDQ
) pins are used to decouple
output noise from the internal circuits and are 2.5 V and 1.8 V
compatible.
Functional Description
Applications
The GS881E18/32/36B(T/D)-xxxV is a 9,437,184-bit high
performance synchronous SRAM with a 2-bit burst address
counter. Although of a type originally developed for Level 2
Cache applications supporting high performance CPUs, the
device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip
set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Paramter Synopsis
-250
-200
3.0
5.0
170
195
6.5
6.5
140
160
-150
3.8
6.7
140
160
7.5
7.5
128
145
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Pipeline
3-1-1-1
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
t
KQ
tCycle
Curr (x18)
Curr (x32/x36)
3.0
4.0
200
230
5.5
5.5
160
185
Flow Through
2-1-1-1
Rev: 1.00 6/2006
1/36
漏 2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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