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GS88136T-66 Datasheet

  • GS88136T-66

  • x36 Fast Synchronous SRAM

  • 610.46KB

  • 33頁

  • ETC

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Preliminary
GS88118/36T-11/11.5/100/80/66
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
鈥?FT pin for user-configurable flow through or pipelined operation
鈥?Single Cycle Deselect (SCD) Operation
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?On-chip write parity checking; even or odd selectable
鈥?3.3 V +10%/鈥?% core power supply
鈥?2.5 V or 3.3 V I/O supply
鈥?LBO pin for Linear or Interleaved Burst mode
鈥?Internal input resistors on mode pins allow floating mode pins
鈥?Default to Interleaved Pipeline mode
鈥?Byte Write (BW) and/or Global Write (GW) operation
鈥?Common data inputs and data outputs
鈥?Clock Control, registered, address, data, and control
鈥?Internal self-timed write cycle
鈥?Automatic power-down for portable applications
鈥?100-lead TQFP package
-11
-11.5
-100
-80
-66
10 ns
10 ns 12.5 ns 15 ns
Pipeline tCycle 10 ns
3-1-1-1
t
KQ
4.0 ns 4.0 ns 4.0 ns 4.5 ns 5.0 ns
I
DD
225 mA 225 mA 225 mA 200 mA 185 mA
Flow
t
KQ
11 ns 11.5 ns 12 ns
14 ns
18 ns
Through tCycle 15 ns
15 ns
15 ns
15 ns
20 ns
2-1-1-1
I
DD
180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 36 ByteSafe鈩?/div>
100 MHz鈥?6 MHz
3.3 V V
DD
8Mb Sync Burst SRAMs
3.3 V and 2.5 V I/O
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode pin (Pin 14). Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the Data
Output Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD Pipelined Reads
The GS88118//36T is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are also
available. SCD SRAMs pipeline deselect commands one stage less
than read commands. SCD RAMs begin turning off their outputs
immediately after the deselect command has been captured in the
input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx). In
addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the byte write control inputs.
ByteSafe鈩?Parity Functions
The GS88118/36T features ByteSafe data security functions. See
detailed discussion following.
Sleep Mode
Functional Description
Applications
The GS88118//36T is a 9,437,184-bit high performance synchronous
SRAM with a 2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in synchronous
SRAM applications, ranging from DSP main store to networking chip
set support.
Low power (Sleep mode) is attained through the assertion (high) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS88118//36T operates on a 3.3 V power supply, and all inputs/
outputs are 3.3 V- and 2.5 V-compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
Rev: 1.10 7/2000
1/33
漏 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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GS88136T-66相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    8Mb Sync Burst SRAMs
    ETC
  • 英文版
    512K x 18, 256K x 36 ByteSafe?? 8Mb Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    GSI Technology [512K x 18, 256K x 36 8Mb S/DCD Sync Burst S...
    GSI
  • 英文版
    512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    256K x 36 9Mb Sync Burst SRAM
    GSI [GSI T...
  • 英文版
    512K x 18, 256K x 32, 256K x 36 8Mb Sync Burst SRAMs
    GSI [GSI T...
  • 英文版
    GSI Technology [512K x 18, 256K x 36 8Mb Sync Burst SRAMs]
    GSI
  • 英文版
    512K x 18, 256K x 36 9Mb Synchronous Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
    GSI
  • 英文版
    512K x 18, 256K x 36 ByteSafe 8Mb Sync Burst SRAMs
    GSI [GSI Techno...
  • 英文版
    9Mb Pipelined and Flow Through Synchronous NBT SRAM
    ETC
  • 英文版
    9Mb Pipelined and Flow Through Synchronous NBT SRAM
    ETC [ETC]
  • 英文版
    GSI Technology [8Mb Pipelined and Flow Through Synchronous ...
    GSI
  • 英文版
    GSI Technology [512K x 18, 256K x 36 9Mb SCD/DCD Sync Burst...
    GSI
  • 英文版
    GSI Technology [256K x 36 9Mb Synchronous Burst SRAMs]
    GSI
  • 英文版
    256K x 36 9Mb SCD/DCD Sync Burst SRAM
    GSI [GSI Techno...

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