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GS880V37AT-200I Datasheet

  • GS880V37AT-200I

  • 256K x 36 9Mb Sync Burst SRAMs

  • 18頁(yè)

  • GSI

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GS880V37AT-250/225/200
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
鈥?Single Cycle Deselect (SCD) operation
鈥?1.8 V +10%/鈥?0% core power supply
鈥?1.8 V I/O supply
鈥?LBO pin for Linear or Interleaved Burst mode
鈥?Internal input resistors on mode pins allow floating mode pins
鈥?Default to Interleaved Pipeline mode
鈥?Byte Write (BW) and/or Global Write (GW) operation
鈥?Internal self-timed write cycle
鈥?Automatic power-down for portable applications
鈥?JEDEC-standard 100-lead TQFP package
256K x 36
9Mb Sync Burst SRAMs
250 MHz鈥?00 MHz
1.8 V V
DD
1.8 V I/O
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
SCD Pipelined Reads
The GS880V37AT is a SCD (Single Cycle Deselect) pipelined
synchronous SRAM. DCD (Dual Cycle Deselect) versions are
also available. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS880V37AT operates on a 1.8 V power supply. All input
are 1.8 V compatible. Separate output power (V
DDQ
) pins are
used to decouple output noise from the internal circuits and are
1.8 V compatible.
Functional Description
Applications
The GS880V37AT is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV), and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
Parameter Synopsis
Pipeline
3-1-1-1
1.8 V
t
KQ
tCycle
Curr
(x36)
-250
2.5
4.0
320
-225
2.7
4.4
295
-200
3.0
5.0
265
Unit
ns
ns
mA
Rev: 1.03 7/2004
1/18
漏 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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