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GS8170LW72C-333I Datasheet

  • GS8170LW72C-333I

  • 18Mb sigma 1x1Lp CMOS I/O Late Write SigmaRAM

  • 27頁

  • ETC

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GS8170LW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Features
鈥?Late Write mode, Pipelined Read mode
鈥?JEDEC-standard SigmaRAM
鈩?/div>
pinout and package
鈥?1.8 V +150/鈥?00 mV core power supply
鈥?1.8 V CMOS Interface
鈥?ZQ controlled user-selectable output drive strength
鈥?Dual Cycle Deselect
鈥?Burst Read and Write option
鈥?Fully coherent read and write pipelines
鈥?Echo Clock outputs track data output drivers
鈥?Byte write operation (9-bit bytes)
鈥?2 user-programmable chip enable inputs
鈥?IEEE 1149.1 JTAG-compliant Serial Boundary Scan
鈥?209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
鈥?Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
18Mb
危
1x1Lp CMOS I/O
Late Write SigmaRAM鈩?/div>
Functional Description
200 MHz鈥?33 MHz
1.8 V V
DD
1.8 V I/O
SigmaRAM Family Overview
GS8170LW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
危
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
危
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
危
RAM
鈩?/div>
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
危
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.6 ns
Rev: 2.03 1/2005
1/27
漏 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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