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GS8162Z36BB-150 Datasheet

  • GS8162Z36BB-150

  • 18Mb Pipelined and Flow Through Synchronous NBT SRAM

  • 34頁(yè)

  • GSI

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GS8162Z18/36B(B/D)
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
鈥?NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM鈩? NoBL鈩?and
ZBT鈩?SRAMs
鈥?2.5 V or 3.3 V +10%/鈥?0% core power supply
鈥?2.5 V or 3.3 V I/O supply
鈥?User-configurable Pipeline and Flow Through mode
鈥?ZQ mode pin for user-selectable high/low output drive
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?On-chip write parity checking; even or odd selectable
鈥?On-chip parity encoding and error detection
鈥?LBO pin for Linear or Interleave Burst mode
鈥?Pin-compatible with 2M, 4M, and 8M devices
鈥?Byte write operation (9-bit Bytes)
鈥?3 chip enable signals for easy depth expansion
鈥?ZZ Pin for automatic power-down
鈥?JEDEC-standard 119-bump and 165-bump BGA packages
鈥?RoHS-compliant 119-bump and 165-bump BGA packages
available
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz鈥?50 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8162Z18/36B(B/D) may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8162Z18/36B(B/D) is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
Functional Description
The GS8162Z18/36B(B/D) is an 18Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x36)
2.5
4.0
295
345
5.5
5.5
225
255
-200
3.0
5.0
245
285
6.5
6.5
200
220
-150
3.8
6.7
200
225
7.5
7.5
185
205
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.04a 2/2006
1/34
漏 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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