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GS816273C-225I Datasheet

  • GS816273C-225I

  • 256K x 72 18Mb S/DCD Sync Burst SRAMs

  • 25頁

  • GSI

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GS816273C-250/225
209-Pin BGA
Commercial Temp
Industrial Temp
Features
鈥?Single/Dual Cycle Deselect selectable
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?ZQ mode pin for user-selectable high/low output drive
鈥?2.5 or 3.3 V +10%/鈥?0% core power supply
鈥?2.5 V or 3.3 V I/O supply
鈥?LBO pin for Linear or Interleaved Burst mode
鈥?Internal input resistors on mode pins allow floating mode pins
鈥?Byte Write (BW) and/or Global Write (GW) operation
鈥?Internal self-timed write cycle
鈥?Automatic power-down for portable applications
鈥?JEDEC-standard 209-bump BGA package
256K x 72
18Mb S/DCD Sync Burst SRAMs
250 MHz鈥?25 MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
SCD and DCD Pipelined Reads
The GS816273C is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one
stage less than read commands. SCD RAMs begin turning off
their outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the
SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
FLXDrive鈩?/div>
The ZQ pin allows selection between high drive strength (ZQ
low) for multi-drop bus applications and normal drive strength
(ZQ floating or high) point-to-point applications. See the
Output Driver Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS816273C operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output
power (V
DDQ
) pins are used to decouple output noise from the
internal circuits and are 3.3 V and 2.5 V compatible.
Functional Description
Applications
The GS816273C is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Parameter Synopsis
-250
Pipeline
3-1-1-1
3.3 V
2.5 V
t
KQ
tCycle
Curr (x72)
Curr (x72)
2.6
4.0
430
410
-225
2.6
4.5
400
375
Unit
ns
ns
mA
mA
Rev: 1.03 7/2004
1/25
漏 2002, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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