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GS8161Z18T-180T Datasheet

  • GS8161Z18T-180T

  • x18 Fast Synchronous SRAM

  • 33頁(yè)

  • ETC

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Preliminary
GS8161Z18/36T-200/180/166/150/133
100 Pin TQFP
Commercial Temp
Industrial Temp
Features
鈥?User configurable Pipelined and Flow through mode.
鈥?NBT (No Bus Turn Around) functionality allows zero wait Read-
Write-Read bus utilization. Fully pin compatible with both pipelined
and flow through NtRAM鈩? NoBL鈩?and ZBT鈩?SRAMs.
鈥?IEEE 1149.1 JTAG Compatible Boundary Scan.
鈥?On-Chip Write Parity Checking. Even or odd selectable.
鈥?2.5V +10%/-5% Core power supply
鈥?2.5V or 3.3V I/O supply.
鈥?3.3V Compatible Inputs.
鈥?LBO pin for linear or interleave burst mode.
鈥?Pin compatible with 2M, 4M and 8M devices.
鈥?Byte write operation. (9 bit Bytes).
鈥?3 chip enable signals for easy depth expansion.
鈥?Clock Control, registered, address, data, and control.
鈥?ZZ Pin for automatic power-down.
鈥?JEDEC standard 100-lead TQFP package.
-200
-180
-166
-150
-133
Pipeline
tCycle 5ns
5.5ns
6ns
6.6ns 7.5ns
3-1-1-1
t
KQ
3.0ns 3.2ns 3.5ns 3.8ns 4.0ns
(x36)
I
DD
390mA 360mA 330mA 300mA 270mA
7.5ns
8ns
8.5ns 10ns 11ns
Flow Through t
KQ
2-1-1-1
10ns
10ns
10ns 15ns
tCycle 10ns
(x36)
I
DD
275mA 275mA 275mA 275mA 195mA
16Mb Pipelined and Flow through
Synchronous NBT SRAM
200Mhz - 133Mhz
2.5V VDD
2.5V or 3.3V I/O
late write or flow through read / single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the need to
insert deselect cycles when the device is switched from read to write
cycles.
Because it is a synchronous device, address, data inputs, and read/
write control inputs are captured on the rising edge of the input clock.
Burst order control (LBO) must be tied to a power rail for proper
operation. Asynchronous inputs include the sleep mode enable, ZZ
and Output Enable. Output Enable can be used to override the
synchronous control of the output drivers and turn the RAM's output
drivers off at any time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation required by asynchronous
SRAMs and simplifies input signal timing.
The GS8161Z18/36T may be configured by the user to operate in
pipelined or flow through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device incorporates
a rising edge triggered output register. For read cycles, pipelined
SRAM output data is temporarily stored by the edge triggered output
register during the access cycle and then released to the output
drivers at the next rising edge of clock.
The GS8161Z18/36T is implemented with GSI's high performance
CMOS technology and is available in a JEDEC Standard 100 pin
TQFP package.
Functional Description
The GS8161Z18/36T is a 16M bit Synchronous Static SRAM. GSI's
NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read / double
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
Read/Write
A
R
B
W
Q
A
C
R
D
B
Q
A
1/33
D
W
Q
C
D
B
E
R
D
D
Q
C
F
W
Q
E
D
D
Q
E
Flow Through
Data I/O
Pipelined
Data I/O
Rev: 2.05 6/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
漏 1998, Giga Semiconductor, Inc.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
This Material Copyrighted by Its Respective Manufacturer

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