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GS8161Z18BD-150IV Datasheet

  • GS8161Z18BD-150IV

  • 18Mb Pipelined and Flow Through Synchronous NBT SRAM

  • 1514.72KB

  • 35頁

  • GSI

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Preliminary
GS8161ZxxB(T/D)-xxxV
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
鈥?User-configurable Pipeline and Flow Through mode
鈥?NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
鈥?Fully pin-compatible with both pipelined and flow through
NtRAM鈩? NoBL鈩?and ZBT鈩?SRAMs
鈥?IEEE 1149.1 JTAG-compatible Boundary Scan
鈥?1.8 V or 2.5 V core power supply
鈥?1.8 V or 2.5 V I/O supply
鈥?LBO pin for Linear or Interleave Burst mode
鈥?Pin-compatible with 2M, 4M, and 8M devices
鈥?Byte write operation (9-bit Bytes)
鈥?3 chip enable signals for easy depth expansion
鈥?ZZ pin for automatic power-down
鈥?JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
packages
鈥?RoHS-compliant TQFPand BGA packages available
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz鈥?50 MHz
1.8 V or 2.5 V V
DD
1.8 V or 2.5 V I/O
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161ZxxB(T/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8161ZxxB(T/D)-xxxV is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 100-pin TQFP and 165-bump FP-BGA packages.
Functional Description
The GS8161ZxxB(T/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
Parameter Synopsis
-250
Pipeline
3-1-1-1
t
KQ
(x18/x36)
tCycle
Curr
(x18)
Curr
(x32/x36)
t
KQ
tCycle
Curr
(x18)
Curr
(x32/x36)
3.0
4.0
280
330
5.5
5.5
210
240
-200
3.0
5.0
230
270
6.5
6.5
185
205
-150
3.8
6.7
185
210
7.5
7.5
170
190
Unit
ns
ns
mA
mA
ns
ns
mA
mA
Flow Through
2-1-1-1
Rev: 1.01a 6/2006
1/35
漏 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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