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SMPTE 292M, SMPTE 344M and SMPTE 259M
compliant
automatic cable equalization
multi-standard operation from 143Mb/s to
1.485Gb/s
supports DVB-ASI at 270Mb/s
manual bypass (useful for low data rates with slow
rise/fall times)
performance optimized for 270Mb/s and 1.485Gb/s
typical maximum equalized length of Belden 1694A
cable: 140m at 1.485Gb/s, 350m at 270Mb/s
50惟 differential output (with internal 50惟 pull-ups)
Pb-free and RoHS Compliant
Description
The GS1524 is a second-generation high-speed bipolar
integrated circuit designed to equalize and restore
signals received over 75惟 co-axial cable at data rates
from 143Mb/s up to 1.485Gb/s. The GS1524 is
designed to support SMPTE 292M, SMPTE 344M and
SMPTE 259M, and is optimized for performance at
270Mb/s and 1.485Gb/s.
The GS1524 features DC restoration to compensate for
the DC content of SMPTE pathological test patterns.
The GS1524 also incorporates a Cable Length Indicator
(CLI) that provides an indication of the amount of cable
being equalized for data rates up to 360Mb/s.
A voltage programmable mute threshold (MCLADJ) is
included to allow muting of the GS1524 output when an
approximate selected cable length is reached for
SMPTE 259M signals. This feature allows the GS1524
to distinguish between low amplitude SD-SDI signals
and noise at the input of the device. The CD/MUTE pin
provides an indication of the GS1524 mute status in
addition to functioning as a mute control input. The SD
outputs of the GS1524 may be forced to a mute state by
applying a voltage to the CD/MUTE pin.
Power consumption is typically 265mW using a 3.3V
power supply.
This component and all homogeneous subcomponents
are RoHS compliant.
Key Specifications
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cable length indicator for SMPTE 259M inputs
output mute based on max cable length adjust or
manual override
single 3.3V power supply operation
operating temperature range: 0擄C to +70擄C
Applications
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SMPTE 292M, SMPTE 344M and SMPTE 259M
Coaxial Cable Serial Digital Interfaces
MCLADJ
CABLE LENGTH INDICATOR/ADJUSTOR
CARRIER DETECT
MUTE
CLI
CD/MUTE
BYPASS
SDI
SDI
EQUALIZER
DC RESTORE
OUTPUT
SDO
SDO
AGC
Functional Block Diagram
14976 - 7
June 2005
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