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GM82C765B Datasheet

  • GM82C765B

  • FLOPPY DISK SUBSYSTEM CONTROLLER

  • 222.95KB

  • 36頁

  • HYNIX

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GM82C765B
GM82C765B
FLOPPY DISK SUBSYSTEM CONTROLLER
General Description
The GM82C765B is a CMOS LSI device which interfaces a host
microprocessor to the floppy disk drive. It integrates the function of the
Formatter/Controller, Data Separator. Write Precompensation, Data rate
selection, Clock Generation, High Current Output Drivers, and TTL
compatible Schmitt Trigger Receivers. The GM82C765B consists of a
microprocessor interface, a microsequencer and a disk drive interface.
The host microprocessor interface of the GM82C765B supports a
12MHz, 286 microprocessor bus without the use of wait states. All inputs
within host microprocessor are Schmitt triggers, except for the data bus,
XTAL, and the host output sink 12mA.
Output drive capability is 20 LSTTL load, allowing direct
interconnection to bus structures without the use of buffers or transceivers.
On the disk drive interface, the GM82C765B includes data seperation that
has been designed to address high performance error rate on floppy disk
drives, and contains all the necessary logic to achieve classical 2nd order,
type2, phase locked loop performance. Write precompensation is included,
in addition to the usual formatting, encoding, decoding, step motor control,
and status sensing functions For PC/XT and PC/AT applications, the
device provides qualification of interrupt and DMA requests.
The disk drive interface of the GM82C765B connects directly to up to
four drives. All drive-related inputs are Schmitt triggers and the drive
outputs are open drain, and sink 48 mA.
The GM82C765B uses two clock inputs which provide the necessary
signals for internal timing. A 16MHz oscillator controls the data rate of
500, 250 and 125Kbits/sec, while a 9.6MHz oscillator controls the
300Kbit/sec data rate used in PC/AT designs.
The two XTAL oscillator circuits may be used for the 44-pin PLCC
package, while TTL clock inputs must be provided when using the 40-pin
DIP package.
In the PLCC version of the GM82C765B pins 17 and 40, which were
not utilized in DIP version of the GM82C765B, became
DCHGEN
(Disk
Change Enable) and
DCHG
(Disk Change) respectively. Both are active
LOW.
DCHGEN
is offered as an option for those designs that used the
original GM82C765B part where
DCHG
did not exist as direct into the
chip.
The GM82C765B has eight internal Registers. The 8 bit main status
register contains status information of the GM82C765B and may be
accessed any time. Another four status register under system control also
give various status and error information. The Control Register provides
support logic that latches the two LSBs used to select the desired data rate
that controls internal clock generation. The Operations Register replaces
the standard latched port used in floppy subsystem.
鈭?/div>
IBM PC compatible format
(single and double density)
鈥?Floppy disk control and
operations on chip
鈥?In PC AT mode, provides required
signal qualification DMA channel
鈥?BIOS compatible and dual speed
Spindle Drive support
鈭?/div>
Integrates Formatter/Controller/Data
Separation, Write Precompensation,
Data rate Selection, Clock
Generation, and drive interface
Drivers and Receivers into one chip
鈭?/div>
Multisector and Multitrack transfer
capability.
鈭?/div>
Direct Floppy Disk Drive interface
with no buffers needed
鈥?48mA sink output drivers
鈥?Schmitt trigger Line Receivers
鈭?/div>
Enhanced Host Interface:
鈥?Supports 12MHz, 286 u-processor
鈥?Capable of driving 20 LSTTL
Load
鈭?/div>
Address mark detection circuitary
internal to Floppy Disk Controller
鈭?/div>
On chip Clock Generation
Two TTL Clock Inputs for 40-DIP
鈭?/div>
Two XTAL oscillator circuits for
44-Quad, PLCC
鈭?/div>
User programmable Track Stepping
Rate and Head load/unload time
鈭?/div>
Drivers up to four Floppy or micro
Floppy Disk Drives
鈭?/div>
Data transfer DMA or non-DMA
mode
鈭?/div>
Parallel seek operations on up to
four Drives
鈭?/div>
Internal power up reset circuitry
鈭?/div>
READ/WRITE access compatible
register with 8 or 12MHz 286
microprocessor with 0 wait states.
鈭?/div>
DMA timing corrected.
鈭?/div>
LOW POWER CMOS, +5V SUPPLY
Features
1

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