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LG Semicon Co.,Ltd.

Description

The GM76C8128CL/CLL-W is a 1,048,576 bits

static random access memory organized as 131,072

words by 8 bits. Using a 0.6um advanced CMOS

technology and operated from a single 2.7V to 5.5V

supply. Advanced circuit technique provide both high

speed and low power consumption. The device is

placed in a low power standby mode with /CS1 high

or CS2 low and the output enable (/OE) allows fast

memory access. Thus it is suitable for high speed and

low power applications, especially where battery

back-up is required.

GM76C8128CL/CLL-W

131,072 WORDS x 8 BIT

CMOS STATIC RAM

Pin Configuration

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O0

I/O1

I/O2

V

SS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

V

CC

A15

CS2

/WE

A13

A8

A9

A11

/OE

A10

/CS1

I/O7

I/O6

I/O5

I/O4

I/O3

Features

* Fast Speed : 55/70ns at Vcc=5V

+/-

10%

120/150ns at Vcc=3V

+/-

10%

* Low Power Standby and Low Power Operation

-Standby : 0.11mW Max. at Vcc=5V

+/-

10%

49.5uW Max. at Vcc=3V

+/-

10%

-Operation : 385mW Max. at Vcc=5V

+/-

10%

66mW Max. at Vcc=3V

+/-

10%

* Completely Static RAM : No Clock or Timing

Strobe Required

* Equal Access and Cycle Time

* TTL compatible inputs and outputs

* Capability of Battery Back-up Operation

* Single +2.7V ~ +5.5V Operation

* Standard 32 DIP, SOP and TSOP I

(Top View)

Block Diagram

A0

A1

A2

Pin Description

Pin

A0-A16

/WE

/CS1, CS2

/OE

I/O0-I/O7

V

CC

V

SS

NC

Function

Address Inputs

Write Enable Input

Chip Select Input

Output Enable Input

Data Inputs/Outputs

/OE

/CS1

CS2

A14

A15

A16

Address

Buffer

128 x 8

7

Y

Decorder

128

/CS1, CS2

Chip

Control

/OE, /WE

Chip

Control

........

10

1024 MEMORY CELL ARRAY

X

1024 x 128 x 8

Decoder

(128K x 8)

Column Select

8

Power Supply (2.7V~5.5V)

Ground

I/O Buffer

/WE

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

121

I/O7

No Connection

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