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GE28F128L30B110 Datasheet

  • GE28F128L30B110

  • 1.8 Volt Intel StrataFlash㈢ Wireless Memory with 3.0-...

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  • INTEL   INTEL

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1.8 Volt Intel StrataFlash Wireless
Memory with 3.0-Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
廬
Datasheet
Product Features
鈻?/div>
High performance Read-While-Write/Erase
鈥?85 ns initial access
鈥?52MHz with zero wait state, 17 ns clock-to-data
output synchronous-burst mode
鈥?25 ns asynchronous-page mode
鈥?4-, 8-, 16-, and continuous-word burst mode
鈥?Burst suspend
鈥?Programmable WAIT configuration
鈥?Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 碌s/byte (Typ)
鈥?1.8 V low-power buffered and non-buffered
programming @ 10 碌s/byte (Typ)
鈻?/div>
Architecture
鈥?Asymmetrically-blocked architecture
鈥?Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
鈥?Multiple 16-Mbit partitions: 256Mb devices
鈥?Four 16-KWord parameter blocks: top or
bottom configurations
鈥?64K-Word main blocks
鈥?Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
鈥?Status register for partition and device status
鈻?/div>
Power
鈥?1.7 V - 2.0 V V
CC
operation
鈥?I/O voltage: 2.2 V - 3.3 V
鈥?Standby current: 30 碌A(chǔ) (Typ)
鈥?4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
鈥?Automatic Power Savings (APS) mode
鈻?/div>
Software
鈥?20 碌s (Typ) program suspend
鈥?20 碌s (Typ) erase suspend
鈥?Intel廬 Flash Data Integrator (FDI) optimized
鈥?Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
鈥?Common Flash Interface (CFI) capable
鈻?/div>
Security
鈥?OTP space:
鈥?64 unique device identifier bits
鈥?64 user-programmable OTP bits
鈥?Additional 2048 user-programmable OTP
bits
鈥?Absolute write protection: V
PP
= GND
鈥?Power-transition erase/program lockout
鈥?Individual zero-latency block locking
鈥?Individual block lock-down
鈻?/div>
Quality and Reliability
鈥?Expanded temperature: 鈥?5擄 C to +85擄 C
鈥?Minimum 100,000 erase cycles per block
鈥?ETOX鈩?VIII process technology (0.13 碌m)
鈻?/div>
Density and Packaging
鈥?64-, 128- and 256-Mbit density in VF BGA
packages
鈥?128/0, and 256/0 Density in Stacked-CSP
鈥?16-bit wide data bus
Intel StrataFlash
廬
memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background.
The
1.8 Volt Intel StrataFlash
廬
wireless memory with 3-Volt
I/O device is manufactured using Intel
0.13 碌m ETOX鈩?VIII process technology. It is available in industry-standard chip scale packaging.
.
The 1.8 Volt Intel StrataFlash
廬
wireless memory with 3-Volt
I/O product is the latest generation of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251903-003
April 2003
Notice:
This document contains information on products in the design phase of

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