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GD65232PWR Datasheet

  • GD65232PWR

  • MULTIPLE RS-232 DRIVERS AND RECEIVERS

  • 18頁

  • TI

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GD65232, GD75232
MULTIPLE RS 232 DRIVERS AND RECEIVERS
SLLS206J 鈭?MAY 1995 鈭?REVISED NOVEMBER 2004
D
Single Chip With Easy Interface Between
D
D
D
UART and Serial-Port Connector of IBM錚?/div>
PC/AT and Compatibles
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Designed to Support Data Rates up to
120 kbit/s
Pinout Compatible With SN75C185 and
SN75185
GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
description/ordering information
V
DD
RA1
RA2
RA3
DY1
DY2
RA4
DY3
RA5
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
GND
The GD65232 and GD75232 combine three
drivers
and
five
receivers
from
the
Texas Instruments trade-standard SN75188 and
SN75189 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design
of the SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection
of the UART and serial-port connector of an IBM錚?PC/AT and compatibles. The bipolar circuits and processing
of the GD65232 and GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent
power and external passive components relative to the SN75C185.
The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28
standards. These standards are for data interchange between a host computer and a peripheral at signaling
rates up to 20 kbit/s. The switching speeds of these devices are fast enough to support rates up to 120 kbit/s
with lower capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected
unless the designer has design control of the cable and the interface circuits at both ends. For interoperability
at signaling rates up to 120 kbit/s, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards
is recommended.
ORDERING INFORMATION
TA
PDIP (N)
SOIC (DW)
鈭?0擄C to 85擄C
SSOP (DB)
TSSOP (PW)
PDIP (N)
SOIC (DW)
0擄C to 70擄C
SSOP (DB)
TSSOP (PW)
PACKAGE鈥?/div>
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
ORDERABLE
PART NUMBER
GD65232N
GD65232DW
GD65232DWR
GD65232DBR
GD65232PW
GD65232PWR
GD75232N
GD75232DW
GD75232DWR
GD75232DBR
GD75232PW
GD75232PWR
GD75232
GD75232
GD75232
GD65232
GD75232N
GD65232
GD65232
TOP-SIDE
MARKING
GD65232N
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM is a trademark of International Business Machines Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2004, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

GD65232PWR 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 接口 - 驅(qū)動器，接收器，收發(fā)器

  • GD

  • 收發(fā)器

  • 3/5

  • RS232

  • 4.5 V ~ 5.5 V

  • 表面貼裝

  • 20-TSSOP（0.173"，4.40mm 寬）

  • 20-TSSOP

  • 帶卷 (TR)

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